Application of Ternary Logic and Delta Modulation in Digital Filter Realization

A new realization of non-recursive digital filters using operation on ternary delta modulated signal is proposed. Direct operation on ternary delta modulated signal will be derived mathematically and a hardware implementation of ternary arithmetic operation will be shown. The primary advantage of the ternary scheme is the simplicity of the hardware and reduction in connections and interconnections between chips and interchips. The results show the possibility of applying ternary arithmetic operation in variety of areas including VLSI environment. INTRODUCTION Delta modulation has been discovered for many years. Due to its simplicity in realization and relatively insensitivity to interference, many investigators have been working on developing various delta modulation systems and their applications. Although complete delta modulation systems were developed quite late and relative attention has been given to the application of delta modulation to digita1 signa1 processing and communications, digital filter realization based on delta modulation is still very attractive. Several realizations of digital filters using delta modulation have been proposed, they show great advantage over conventional realization of digital filter based on PCM technology. However, these realizations all use classical binary logic for A/D conversion and its implementation. Binary system, of course, has its advantage but also has its disadvantage when compared with high radix logic system. First, in binary system, one signal line can only carry one bit signal which is either 0 or 1. This will greatly reduce and limit the signal-carrying capability as well as signal processing capability. When we realize a desired logic function in VLSI technology, this will become the limit to the minimum possible size of a chip. We finally will reach the point where further scaling down a signal processing chip is not possible. Second, in VLSI technology the major problems are associated with the complexity of the connections between components on a chip and the interconnections between chips, since information which could be processed by a chip is proportional to the chip area, but information which could be transferred to the chip by the connecting points is proportional to the chip perimeter. Now the area of a chip increases proportionally to the square of the chip perimeter and the chip perimeter (i.e. the number of pins) becomes the limiting factor in the information processing rather than the chip area. Connection are expensive -they introduce the usual noise and reliability problems and require expensive testing. As a result, the cost of components is a relatively small part of the tota1 price of th e system, while the complexity of interconnections between subsystems dictates the overall cost of the system. In our case where we use delta modulation technology to realize a digital filter the situation described above becomes more severe: a great number of registers, adders, multipliers, and other devices, rather complicated connections and interconnections, make a VLSI chip design for the filter very difficult, if not impossible. The main issue here is that: Is it possible for one signal line to carry more than one bit information and is it possible for each device to perform more computation? The application of multiple-valued logic and the use of multiple-level delta modulation in digital processing is one way of increasing the information rate per wire , which will lead to a simple inexpensive digital fitler implementation where delta modulator acts as a basic A/D convertor and addition and subtraction are carried out in symmetrical non-redundant multiple-valued logic number system. TERNARY NUMBER REPRESENTATION AND TERNARY FULL ADDER In this paper we consider a symmetrical ternary non-redundant number representation in which the ternary digits are coded as +1, 0, !1. The idea of using ternary logic is not new. The system scientists and engineers who worked on hard problems of synthesis (analysis of a given system is always easier) have asked many times over whether binary logic is optimal. In practice situations frequently arise where binary answer of YES/NO is not sufficient. We would prefer at times a logic systems with statements such as YES/NO/NOT, UP/DOWN/STOP, or RIGHT/LEFT/STRAIGHT-AHEAD. It is obvious that for such realization we would need three valued (radix 3) digital realization. In fact, it has been shown that three is the “best” radix to use, and this also leads to increase of the amount of information per signal line by a factor of 1.585. The symmetric ternary nonredundant number representation is of great interest to digital filter realization. Signconversion and special round-off technique are not required, and addition and subtraction carried out without regard to sign . Since the full adder is the base for the subtractor and the multiplier in any radix number system, it is the basic building block in digital signal processing. Thus we first consider the definition of ternary full adder and its mathematical model. Definition: A ternary full adder is a 3-input and 2-output device which maps input set (3 elements, Xn, Yn, Cn!1) into output set (2 elements, Sn, Cn), where all these elements take values of symmetric ternary non-redundant number, ie. Xn, Yn, Cn!1, Sn, Cn ,{!1, 0, 1 }. The ternary full adder block diagram is shown in Figure 1. Xn, Yn, Cn!1, Sn, Cn are named inputs, carry-in, sum and carry-out respectively, as in binary case. Although input set has 3 = 27 combinations, only 7 combinations are needed for output set. This is because permutation law applies to addition and we use symmetric nonredundant ternary number system. For addition of three such numbers (Xn, Yn, Cn!1), only 7 different outcomes are possible, i.e. if we designate Zn = Xn + Yn + Cn!1 then Zn ,{3, 2, 1, 0, !1, !2, !3}. Each of these 7 outcomes can be assigned a different pair (Sn, Cn). There are C9 = 36 possibilities of two ternary delta modulated sequences. They are listed in TABLE 1 and TABLE 2. The two tables can be viewed as the truth tables for ternary full adder. From TABLE 1 we have Sn = 1/3 [ Xn + Yn + Cn!1 ! Cn ] (1) From TABLE 2 we have Sn = 1/3 [ Xn + Yn + Cn!1 + Cn ] (2) Let us consider Sn = 1/3 [ Xn + Yn + Cn!1 ! Cn ] as the basic equation for our ternary full adder throughout the rest of is paper. DIRECT OPERATION ON TERNARY DELTA MODULATED SEQUENCES Delta modulation is a one-bit A/D conversion method, a ternary delta modulator transforms an analog input signal X(t) to a ternary sequence: Xn = . . . . . . X!1, X0, X1 . . . . . . (3) where Xi takes values +1, 0, or !1 at intervals of T-seconds. The feedback path of the system consists of an ideal integrator and an amplifier, much the same as in binary case. The impulse response of the ideal integrator will be a piece-wise linear function. The amplifier has a gain * causing the feedback slope size to be * also. The integrated feedback output signal X(t) is given by